1. Field of the Invention
The present invention relates to a resistive cross-point cell array, and more particularly, to a technique for highly reliably determining data stored in a memory cell of the array.
2. Description of the Related Art
A Magnetic Random Access Memory (hereinafter referred to as an MRAM) and a Resistive Random Access Memory (hereinafter referred to as a ReRAM) have attracted attention as a non-volatile memory which enables high-speed write and a large number of rewritable times. Hereinafter, an MRAM will be described.
A typical MRAM includes an array of memory cells. A word line is extended along each row of memory cells, and a bit line is extended along each column of memory cells. Each memory cell is located at a cross point of a word line and a bit line.
Each memory cell stores 1-bit information as a direction of magnetization. The magnetization of each memory cell has one of two stable directions at any particular time. The two stable directions represent logical values “0” and “1”.
The direction of magnetization has an influence on the resistance of a memory cell as in a spin-dependent tunnel junction device. For example, when the direction of magnetization is parallel, the resistance of a memory cell has a first value R, and when the direction of magnetization is changed from “parallel” to “reverse parallel”, the resistance of the memory cell increases to a second value R+ΔR. The direction of magnetization (i.e., logic state) of a selected memory cell can be read by detecting the resistance of the selected memory cell.
In MRAMs, memory cells are arranged in the following two known manners: magnetic resistance elements are connected via access transistors to bit lines; and magnetic resistance elements are directly connected to word lines and bit lines. The latter arrangement is suitable for higher-density integration, but has a lower level of memory cell selectivity than that of the former arrangement. The memory cell array of the latter arrangement is known as a cross-point cell array.
The reliability of determining data in a memory cell of an MRAM employing a cross-point cell array is impaired by, for example, a parasitic current (or a sneak path current). The memory cells in the cross-point cell array are connected by a large number of parallel paths. The sneak path current refers to a current which flows via the parallel path without passing through a memory cell to be read. The sneak path current hinders accurate detection of the resistance of a memory cell when data stored in the memory cell is determined.
A technique of highly reliably detecting the resistance of a memory cell in a cross-point cell array while suppressing the influence of a sneak path current has been proposed. In this technique, during a read operation with respect to a memory cell in an MRAM, equal potentials are applied to a selected bit line and non-selected bit lines (or non-selected word lines) (see U.S. Pat. No. 6,259,644).
In this technique, however, the potentials applied to a selected bit line and non-selected bit lines (or non-selected word lines) need to be equal to each other with high precision, which is not very practical. Therefore, according to another conventional technique, a current flowing through a dummy cell or a reference cell is subtracted from a current flowing through a selected cell, thereby suppressing the influence of a sneak path current (see U.S. Pat. No. 6,885,579).
FIG. 10 is a diagram showing an exemplary circuit configuration of a conventional MRAM employing dummy cells. The MRAM includes a cross-point cell array 1001, memory cells 1002 arranged in x and y directions, bit lines 1004 extended in the y direction, dummy cells 1008 arranged in the y direction, and a dummy bit line 1009 extended in the y direction. The dummy cells 1008 are provided at cross points of word lines 1003 and the dummy bit line 1009. Each dummy cell 1008 is interposed between one word line 1003 and the dummy bit line 1009 which intersect at the dummy cell 1008. Data of either “1” or “0” is written into each dummy cell 1008. It is important for the dummy cells 1008 to have a stable condition, and data does not necessarily need to be written therein. The dummy cells 1008 contribute to the removal of offset components of currents flowing through the memory cells 1002, thereby increasing an SN ratio during read.
The cross-point cell array 1001 further includes an X selector 1011, a first Y selector 1012, and a second Y selector 1013. The X selector 1011 is connected to the word lines 1003 and selects one (selected word line) of the word lines 1003. The first Y selector 1012 and the second Y selector 1013 are connected to the bit lines 1004 and select one (selected bit line) of the bit lines 1004. One of the memory cells 1002 which is connected to the selected word line and the selected bit line is selected as a selected cell 1002a. Further, one of the dummy cells 1008 which is connected to the selected word line is selected as a selected dummy cell 1008a. The selected dummy cell 1008a is used to remove the offset component of a current flowing through the selected cell 1002a. 
Data stored in the selected cell 1002a is determined by a read circuit 1016. The read circuit 1016 supplies a potential V2′ which is substantially the same as a potential V2 of a second power supply line 1015, to the selected bit line and the dummy bit line 1009, in order to determine the data stored in the selected cell 1002a. On the other hand, the X selector 1011 applies a potential V1 of a first power supply line 1014 to the selected word line. Due to the application of the potential V2′ to the selected bit line, a potential V2′-V1 is applied between the selected bit line and the selected word line, so that a current Is flows through the selected bit line. On the other hand, the potential V2′-V1 is also applied between the dummy bit line 1009 and the selected word line, so that a current Ic flows through the dummy bit line 1009. Since the potential V2 applied to non-selected bit lines is substantially equal to the potential V2′ applied to the selected bit line and the dummy bit line 1009, a sneak path current flowing through the cross-point cell array 1001 is reduced. The read circuit 1016 determines the data stored in the selected cell 1002a based on a difference Is-Ic between the current Is flowing through the selected bit line and the current Ic flowing through the dummy bit line 1009.
The read circuit 1016 is implemented by a subtraction circuit 1017, an I-V conversion circuit 1018, a voltage holding circuit 1019, and a comparator 1020. The subtraction circuit 1017 is connected via the second Y selector 1013 to the selected bit line and the dummy bit line 1009, and generates a current Is-Ic which is obtained by subtracting the offset component current Ic flowing through the dummy bit line 1009 from the detection current Is flowing through the selected bit line. The I-V conversion circuit 1018 converts the current Is-Ic output by the subtraction circuit 1017 into a voltage and outputs the voltage. An output of the I-V conversion circuit 1018 is connected to inputs of the voltage holding circuit 1019 and the comparator 1020. The voltage holding circuit 1019 takes in and holds the voltage output by the I-V conversion circuit 1018 which corresponds to the data stored in the selected cell 1002a, and outputs the held voltage as a first read voltage Vp1. Next, data “0” is written into the selected cell 1002a, and a voltage which is output by the I-V conversion circuit 1018, corresponding to data “0” is a second read voltage Vp2. The comparator 1020 compares the first read voltage Vp1 output by the voltage holding circuit 1019 with the second read voltage Vp2 output by the I-V conversion circuit 1018, thereby determining original stored data of the selected cell 1002a, and generates a data signal SAOUT corresponding to the original stored data. Further, when it is determined that the original stored data is “1”, data “1” is written into the selected cell 1002a (rewrite operation).
In the conventional MRAM of FIG. 10, it is important that the current Is flowing through the selected bit line and the current Ic flowing through the dummy bit line 1009 have offset components whose magnitudes are close to each other. The offset component refers to a current component mainly caused by a sneak path current. The magnitude of the offset component varies depending on states of surrounding memory cells. Therefore, the offset components of the current Is flowing through the selected bit line and the current Ic flowing through the dummy bit line 1009 have a difference. If the difference between the offset components is large, erroneous read occurs. Further, a larger number of dummy cells 1008 need to be provided in the cross-point cell array 1001 in order to reduce the difference between the offset components, resulting in an increase in cell area.
On the other hand, when a predetermined reference current is used to determine data stored in a memory cell of a resistive cross-point cell array, erroneous read occurs as will be hereinafter described with reference to FIGS. 11A to 11C.
FIGS. 11A to 11C are diagrams showing changes in memory cell current Is of a conventional non-volatile semiconductor memory device (distributions of memory cell currents), where the horizontal axis represents memory cell currents and the vertical axis represents the number of memory cells. FIG. 11A shows a distribution of memory cell currents in the absence of a sneak path current. In FIG. 11A, 1101 indicates a distribution of memory cell currents having data “0”, 1102 indicates a distribution of memory cell currents having data “1”, and Ir indicates a predetermined reference current.
FIGS. 11B and 11C are diagrams showing distributions of memory cell currents in the presence of a sneak path current. FIGS. 11B and 11C show how the sneak path current successively increases, and the memory cell current increases due to an increase in the sneak path current. In FIGS. 11B and 11C, 1103 and 1105 indicate distributions of memory cell currents having data “0”, and 1104 and 1106 indicate distributions of memory cell currents having data “1”.
As shown in FIG. 11A, if a memory cell current is smaller than a predetermined reference current Ir, data is determined to be “0”. If a memory cell current is larger than the reference current Ir, data is determined to be “1”. When there is not a sneak path current as shown in FIG. 11A or when there is a small sneak path current as shown in FIG. 11B, data stored in a memory cell can be correctly determined. However, when there is a large sneak path current as shown in FIG. 11C, data “0” is determined to be data “1”, i.e., erroneous read occurs.